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Combination Lock
This circuit uses 4013 D-type bi-stable flip-flops.  
Each flip-flop has a data input, D and a clock input, cl.  
The voltage applied to the D input is transferred to the Q output at the instant when the clock input goes from 0 to 1, (we say these flip-flops are edge-triggered.)  
Switches 1, 2, 3 and 4 are the switches which form the code and any number of "wrong" switches can be connected, in parallel, at the point shown.  
Notice that if any "wrong" switch is pushed, the system is reset for abo ut 10 seconds  
The 220n capacitor ensures that the relay is not activated when the supply to the circuit is first switched on.  
   
 
   
Vero board, copper side  
 
   
Vero board, component side  
 
   
Improved Version:  
One minor limitation of the above circuit is that if a "right" button is pushed at the wrong time, it simply does nothing.  
In the circuit shown below if one of the "right" buttons is pushed at the wrong time, the whole circuit is reset (again, with a delay, if you include the 1 capacitor).  
   
 
   
The flip-flops are again in two 4013 chips and the AND gates are a 4081.  
If you think this extra security is worth having, I'm sure you will be prepared to work out the vero layout for yourself!  
In both these circuits, it is a good idea to use screw connectors to connect the switches (rather than soldering them) so that the combination can be changed relatively easily.  
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